NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 111

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

6.
Datasheet
Figure 14. XOR Tree Implementation
R
Testability
In the GMCH, the testability for Automated Test Equipment (ATE) board level testing has been changed
from the traditional NAND chain mode to a XOR chain. The GMCH pins are grouped in seven XOR
chains.
An XOR-Tree is a chain of XOR gates each with one of its inputs connected to a GMCH input pin or bi-
directional pin (used as an input pin only). The other input of each XOR gate connects to the non-
inverted output of the previous XOR gate in the chain. The first XOR gate of each chain will have one
pin internally connected tied to Vcc. The output of the last XOR gate is the chain output. Figure 14
shows the GMCH XOR chain implementation.
Tri-state GMCH Outputs
When testing other devices in the system, the GMCH outputs can be tri-stated. To tri-state these outputs
pull the LMD30 pin high (3.3V) prior to deasserting RESET#. The following sequence will put the
GMCH into tri-state mode:
No external clocking of the GMCH is required.
1. Deassert RESET# high and LMD30 high
2. Assert RESET# low; maintain LMD30 high
3. Deassert RESET# high; maintain LMD30 high
4. RESET# must be maintained high for the duration of testing.
Pin 1
Vcc
Pin 2
Pin 3
Pin 4
Pin 5
Intel
Pin 6
®
82810E (GMCH)
xor.vsd
XOR
Out
111