NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 60

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
3.5.23.
3.5.24.
60
®
82810E (GMCH)
PM_CAPID    Power Management Capabilities ID Register
PM_CAP    Power Management Capabilities Register (Device 1)
(Device 1)
Address Offset:
Default Value:
Access:
Address Offset:
Default Value:
Access:
15:11
15
15:8
15
7
Bits
Bits
7:0
8:6
2:0
10
9
5
4
3
Reserved
NEXT_PTR. This contains a pointer to next item in capabilities list. This the final capability in the list
and must be set to 00h.
CAP_ID. SIG defines this ID is 01h for power management.
PME Support. This field indicates the power states in which the GMCH may assert PME#. Hardwired
to 0 to indicate that the GMCH does not assert the PME# signal.
D2. Hardwired to 0 to indicate D2 power management state is not supported.
D1. Hardwired to 0 to indicate that D1 power management state is not supported.
Reserved. Read as 0s.
Device Specific Initialization (DSI). Hardwired to 1 to indicate that special initialization of the GMCH
is required before generic class device driver is to use it.
Auxiliary Power Source. Hardwired to 0.
PME Clock. Hardwired to 0 to indicate the GMCH does not support PME# generation.
Version. Hardwired to 001b to indicate there are 4 bytes of power management registers
implemented.
NEXT_PTR
PME Support (HW=0)
6
Specific
(HW=1)
Dev
Init
5
DCh−DDh
0001h
Read Only
DEh−DFh
0021h
Read Only
Aux Pwr
(HW=0)
Src
4
8
Description
Description
7
(HW=0)
Clock
PME
3
11
2
(HW=0)
D2
10
CAP_ID
Version (HW=001)
(HW=0)
D1
9
Reserved
Datasheet
8
0
0
R