NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 59

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

3.5.19.
3.5.20.
3.5.21.
3.5.22.
Datasheet
R
INTRLINE    Interrupt Line Register (Device 1)
INTRPIN    Interrupt Pin Register (Device 1)
MINGNT    Minimum Grant Register (Device 1)
MAXLAT    Maximum Latency Register (Device 1)
Address Offset:
Default Value:
Access:
Address Offset:
Default Value:
Access:
Address Offset:
Default Value:
Access:
Address Offset:
Default Value:
Access:
7:0
7:0
7:0
7:0
Bit
Bit
Bit
Bit
Interrupt Connection. Used to communicate interrupt line routing information. POST software writes
the routing information into this register as it initializes and configures the system. The value in this
register indicates which input of the system interrupt controller that the device’s interrupt pin is
connected to.
Interrupt Pin. As a single function device, GMCH specifies INTA# as its interrupt pin.
01h=INTA#.
Minimum Grant Value. GMCH does not burst as a PCI compliant master.
Bits[7:0]=00h.
Maximum Latency Value. Bits[7:0]=00h. The GMCH has no specific requirements for how often it
needs to access the PCI bus.
3Ch
00h
Read/Write
3Dh
01h
Read Only
3Eh
00h
Read Only
3Fh
00h
Read Only
Descriptions
Descriptions
Descriptions
Descriptions
Intel
®
82810E (GMCH)
59