NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 112

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
6.1.
6.1.1.
112
Table 22. XOR Test Pattern Example
®
82810E (GMCH)
Test Pattern Consideration for XOR Chain 7
XOR TREE Testability Algorithm Example
XOR tree testing allows users to check, for example, opens and shorts to VCC or GND. An example
algorithm to do this is shown in Table 22.
In this example, Vector 1 applies all “0s” to the chain inputs. The outputs being non-inverting, will
consistently produce a “1” at the XOR chain output on a good board. One short to Vcc (or open floating
to Vcc) will cause a “0” at the chain output, signaling a defect.
Likewise, applying Vector 7 (all “1”) to chain inputs (given that there are an even number of signals in
the chain), will consistently produce a “1” at the XOR chain output on a good board. One short to Vss (or
open floating to Vss) will cause a “0” at the chain output, signaling a defect. It is important to note that
the number of inputs pulled to “1” will affect the expected chain output value. If the number chain inputs
pulled to “1” is even, then expect “1” at XOR-out; otherwise, if odd, expect “0”.
Continuing to Illustrate with the example pattern in Table 22, as the pins are driven to “1” across the
chain in sequence, XOR-out will toggle between “0” and “1”. Any break in the toggling sequence (e.g.,
“1011”) will identify the location of the short or open.
Bi-directional pins HLSTRB (chain 7) and HLSTRB# (chain 6) must always be complementary to each
other. For example, if a “1” is driven on to HLSTRB, a “0” must be driven on HLSTRB# and vice versa.
This will need to be considered in applying test patterns to this chain.
Vector
1
2
3
4
5
6
7
PIN1
0
1
1
1
1
1
1
PIN2
0
0
1
1
1
1
1
Pin # from Figure 14
PIN3
0
0
0
1
1
1
1
PIN4
0
0
0
0
1
1
1
PIN5
0
0
0
0
0
1
1
PIN6
0
0
0
0
0
0
1
XOROut
1
0
1
0
1
0
1
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