NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 24

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
2.9.
2.10.
24
Table 1. Power Up Options
Table 2. Host Frequency Strappings
®
82810E (GMCH)
Miscellaneous Interface Signals
Power-Up/Reset Strap Options
Table 1 list power-up options that are loaded into the 82810E GMCH during cold reset.
GTLREFA
GTLREFB
RESET#
LMD[31]
LMD[30]
LMD[29]
LMD[28]
LMD[13]
Signal Name
LMD[13]
Signal
0
0
1
I
Ref
I
Ref
I
XOR Chain Test Select: LMD[31] is set to 0 for normal operation. It must be set to 1 to enter
XOR tree mode during reset. This signal must remain 1 during the entire XOR tree test.
ALL Z select: If LMD[30] is set to 1, it will tri-state all signals during reset. For normal
operation, LMD[30] should be set to 0.
Host Frequency Select: If LMD[13] is 0 and LMD[29] is set to 0 during reset, the host bus
frequency is 66 MHz. If LMD[13] is 0 and LMD[29] is set to 1, the host bus frequency is
100 MHz.
In-Order Queue Depth Status: The value on LMD[28] sampled at the rising edge of
CPURST# reflects if the IOQD is set to 1 or 4. If LMD[28] is set to 0, the IOQD is 4. If
LMD[28] is set to 1, the IOQD is 1.
Host Frequency Select: If LMD[13] is a 0, LMD[29] determines host bus frequency. If
LMD[13] is a 1, host bus frequency is 133 MHz.
Type
LMD[29]
X
0
1
AGTL Reference Voltage: Reference signal to the Host Interface.
AGTL Reference Voltage: Reference signal to the Host Interface.
Global Reset: Driven by the ICH/ICH0 when PCIRST# is active.
Description
Host Bus Frequency
Description
100 MHz
133 MHz
66 MHz
Datasheet
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