NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 5

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

5.
6.
Datasheet
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4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
4.9.
Pinout and Package Information ..............................................................................................103
5.1.
5.2.
Testability..................................................................................................................................111
6.1.
6.2.
6.3.
4.1.2.
4.1.3.
4.1.4.
Host Interface.................................................................................................................77
4.2.1.
4.2.2.
System Memory DRAM Interface...................................................................................81
4.3.1.
4.3.2.
4.3.3.
4.3.4.
4.3.5.
Intel
Display Cache Interface .................................................................................................86
4.5.1.
4.5.2.
4.5.3.
4.5.4.
Internal Graphics Device................................................................................................89
4.6.1.
4.6.2.
4.6.3.
4.6.4.
4.6.5.
4.6.6.
4.6.7.
4.6.8.
4.6.9.
4.6.10.
4.6.11.
4.6.12.
4.6.13.
System Reset for the GMCH .......................................................................................101
System Clock Description ............................................................................................101
Power Management .....................................................................................................101
4.9.1.
82810E GMCH Pinout..................................................................................................103
Package Dimensions ...................................................................................................109
XOR TREE Testability Algorithm Example ..................................................................112
6.1.1.
XOR Tree Initialization .................................................................................................113
6.2.1.
6.2.2.
XOR Chain Pin Assignments .......................................................................................114

Dynamic Video Memory Technology (D.V.M.T.) ..................................................86
4.1.1.3.
4.3.1.1.
4.3.1.2.
4.6.7.1.
4.6.7.2.
Memory Shadowing .....................................................................................76
I/O Address Space.......................................................................................76
GMCH Decode Rules and Cross-Bridge Address Mapping ........................77
Host Bus Device Support.............................................................................77
Special Cycles..............................................................................................80
DRAM Organization and Configuration........................................................81
DRAM Address Translation and Decoding ..................................................83
DRAM Array Connectivity ............................................................................85
SDRAMT Register Programming.................................................................85
SDRAM Paging Policy .................................................................................86
Supported DRAM Types ..............................................................................87
Memory Configurations................................................................................87
Address Translation .....................................................................................88
Display Cache Interface Timing ...................................................................88
3D/2D Instruction Processing ......................................................................89
3D Engine ....................................................................................................90
Buffers..........................................................................................................90
Setup............................................................................................................91
Texturing ......................................................................................................92
2D Operation................................................................................................94
Fixed Blitter (BLT) and Stretch Blitter (STRBLT) Engines ...........................94
Hardware Motion Compensation .................................................................95
Hardware Cursor..........................................................................................96
Overlay Engine.............................................................................................96
Display .........................................................................................................96
Flat Panel Interface / 1.8V TV-Out Interface................................................99
DDC (Display Data Channel) .....................................................................100
Specifications Supported ...........................................................................101
Test Pattern Consideration for XOR Chain 7.............................................112
Chain [1:2, 4:7] Initialization .......................................................................113
Chain 3 Initialization ...................................................................................113
System Management Mode (SMM) Memory Range.......................75
Configuration Mechanism For DIMMs.............................................82
DRAM Register Programming.........................................................82
Fixed BLT Engine............................................................................95
Arithmetic Stretch BLT Engine ........................................................95
Intel
®
82810E (GMCH)
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