NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 32

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
3.4.3.
32
®
82810E (GMCH)
PCICMD    PCI Command Register (Device 0)
Address Offset:
Default:
Access:
Size
This 16-bit register provides basic control over the GMCH PCI0 (i.e., Hub-Interface) interface’s ability
to respond to Hub Interface cycles.
15:10
15
Bit
Addr/Data
(Not Impl)
Stepping
9
8
7
6
5
4
3
2
1
0
7
Reserved.
Fast Back-to-Back. (Not implemented; hardwired to 0). Writes to this bit position have no effect
SERR Enable (SERRE). This bit is a global enable bit for Device #0 SERR messaging. The GMCH
does not have an SERR# signal. The GMCH communicates the SERR condition by sending an SERR
message to the ICH. If this bit is set to a 1, the GMCH is enabled to generate SERR messages over
the hub interface for specific Device #0 error conditions (Note: the only SERR condition for the GMCH
is Received Target Abort, therefore there are no other SERR enable bits in the GMCH ). If SERRE is
reset to 0, then the SERR message is not generated by the GMCH for Device #0.
NOTE: This bit only controls SERR messaging for the Device #0.
Address/Data Stepping. (Not implemented; hardwired to 0). Writes to this bit position have no effect.
Parity Error Enable (PERRE). (Not implemented; hardwired to 0). Writes to this bit position have no
effect.
VGA Palette Snoop. (Not implemented, hardwired to 0). Writes to this bit position have no effect
Memory Write and Invalidate Enable. (Not implemented; hardwired to 0). Writes to this bit position
have no effect
Special Cycle Enable. (Not implemented; hardwired to 0). Writes to this bit position have no effect
Bus Master Enable (BME). (Not implemented: hardwired to 1). GMCH is always a Bus Master. Writes
to this bit position have no effect
Memory Access Enable (MAE). (Not implemented; hardwired to 1). Writes to this bit position have no
effect
I/O Access Enable (IOAE). (Not implemented: hardwired to 0). Writes to this bit position have no
effect
(Not Impl)
Error En
Parity
6
(Not Impl)
VGA Pal
Sn
5
Reserved (0)
04–05h
0006h
Read/Write
16 bits
& Inval En
(Not Impl)
Mem WR
4
Descriptions
(Not Impl)
Cycle En
Special
3
Master En
(Not Impl)
Bus
2
10
(Not Impl)
(Not Impl)
AccEn
FB2B
Mem
9
1
I/O AccEn
SERR En
(Not Impl)
Datasheet
8
0
R