NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 33

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

3.4.4.
Datasheet
R
PCISTS    PCI Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
PCISTS is a 16 bit status register that reports the occurrence of error events on the hub interface.
10:9
Bit
6:5
3:0
15
14
13
12
11
Detected
Par Error
8
7
4
(HW=0)
(HW=1)
FB2B
15
7
Detected Parity Error (DPE)—RO. This bit is hardwired to 0. Writes to this bit position have no effect.
Signaled System Error (SSE)—RWC. (Note: the only SERR condition for GMCH is Received Target
Abort; therefore, there are no other SERR enable bits in the GMCH ).
Received Master Abort Status (RMAS)—RWC.
Received Target Abort Status (RTAS)—RWC.
Signaled Target Abort Status (STAS)—RO. (Not implemented; hardwired to a 0). Writes to this bit
position have no effect.
DEVSEL# Timing (DEVT)—RO. These bits are hardwired to “00”. Writes to these bit positions have no
effect. Device #0 does not physically connect to PCI0. These bits are set to “00” (fast decode) so that
optimum DEVSEL timing for PCI0 is not limited by the GMCH.
Data Parity Detected (DPD)—RO. Hardwired to a 0. Writes to this bit position have no effect.
Fast Back-to-Back (FB2B)—RO. Hardwired to 1. Writes to these bit positions have no effect. Device
#0 does not physically connect to PCI. This bit is set to 1 (indicating fast back-to-back capability) so
that the optimum setting for PCI is not limited by the GMCH.
Reserved.
Capability List (CLIST)—RO. This bit is hardwired to 0, to indicate to the configuration software that
this device/function does not implement a new list of features, and that there is NO CAPPTR.
Reserved.
1 = GMCH Device #0 generated an SERR message over hub interface for any enabled Device #0 error
0 = Software sets SSE to 0 by writing a 1 to this bit.
1 = GMCH generated a Hub-Interface request that receives a Master Abort completion packet.
0 = Software clears this bit by writing a 1 to it.
1 = GMCH generated a Hub Interface request that receives a Target Abort completion packet.
0 = Software clears this bit by writing a 1 to it.
condition. Device #0 error conditions are enabled in the PCICMD register. Device #0 error flags are
read/reset from the PCISTS register.
6
Sig Sys
Error
14
Reserved
Mast Abort
Recog
Sta
13
5
06–07h
0080h
Read Only, Read/Write Clear
16 bits
Abort Sta
Cap List
(HW=0)
(HW=0)
Target
Rec
12
4
Descriptions
3
Sig Target
Abort Sta
(HW=0)
11
10
DEVSEL# Timing
Reserved
(HW=00)
Intel
®
82810E (GMCH)
9
Detected
Data Par
(HW=0)
8
0
33