NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 62

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
3.6.
3.6.1.
62
Table 6 Memory Mapped Registers
®
82810E (GMCH)
DRT—DRAM Row Type
Display Cache Interface
The Display Cache (DC) interface control registers are located in memory Space. This section describes
the DC interface registers. These registers are accessed using [MMADR+Offset]. These registers are
memory mapped only. Table 6 contains a list of the memory mapped registers for the 82810E.
Memory Offset Address:
Default Value:
Access:
Size:
This 8-bit register identifies whether or not the display cache is populated. Memory mapped only.
03000h
03001h
03002h
03003-03FFFh
04000-06017h
07000-0FFFFh
7:1
Bit
7
0
Address
Offset
Reserved
DRAM Populated (DP). The bit in this register indicates whether or not the Display Cache is populated.
0 = No Display Cache
1 = 4 MB Display Cache
DRT
DRAMCL
DRAMCH
Register
Symbol



DRAM Row Type
DRAM Control Low
DRAM Control High
Intel Reserved
Intel Reserved
Reserved
3000h
00h
Read / write
8 bit
Reserved
Register Name
Description
17h
08h
Default Value
00h



1
Populated
R/W
R/W
R/W
DRAM
Access
Datasheet
0



R