NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 81

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

4.3.
4.3.1.
Datasheet
R
DRAM Organization and Configuration
System Memory DRAM Interface
The GMCH integrates a system DRAM controller that supports a 64-bit DRAM array. The DRAM type
supported is Synchronous (SDRAM). The GMCH generates the SCS#, SDQM, SCAS#, SRAS#, SWE#
and multiplexed addresses, SMA for the DRAM array. The GMCH’s DRAM interface operates at a
clock frequency of 100 MHz, independent of the system bus interface clock frequency. The DRAM
controller interface is fully configurable through a set of control registers. Complete descriptions of these
registers are given in the Chapter 3, “Configuration Registers”.
The GMCH supports industry standard 64-bit wide DIMM modules with SDRAM devices. The 2 bank
select lines SBS[1:0], the 12 Address lines SMAA[11:0], and second copies of 4 Address lines
SMAB[7:4]# allow the GMCH to support 64-bit wide DIMMs using 16Mb, 64Mb, or 128Mb technology
SDRAMs. The GMCH has four SCS# lines, enabling the support of up to four 64-bit rows of DRAM.
For write operations of less than a QWord in size, the GMCH will perform a byte-wise write. The
GMCH targets SDRAM with CL2 and CL3 and supports both single and double-sided DIMMs. The
GMCH provides refresh functionality with programmable rate (normal DRAM rate is 1 refresh/15.6 µs).
The GMCH can be configured via the Page Closing Policy Bit in the GMCH Configuration Register to
keep multiple pages open within the memory array. Pages can be kept open in any one row of memory.
Up to 4 pages can be kept open within that row (The GMCH only supports 4 Bank SDRAMs on system
DRAM interface).
The GMCH supports 64-bit DRAM configurations. In the following discussion the term row refers to a
set of memory devices that are simultaneously selected by a SCS# signal. The GMCH will support a
maximum of 4 rows of memory. Both single-sided and double-sided DIMMs are supported.
The interface consists of the following pins:
Multiple copies: SMAA[7:4], SMAB[7:4]#
Single Copies:
The GMCH supports DIMMs populated with 8, 16, and 32 bit wide SDRAM devices. Registered
DIMMs or DIMMs populated with 4 bit wide SDRAM devices are not supported. The GMCH supports
3.3V standard SDRAMs.
Table 11 illustrates a sample of the possible DIMM socket configurations along with corresponding DRP
programming. See the register section of this document for a complete DRP programming table.
SMD[63:0]
SDQM[7:0]
SMAA[11:8,3:0]
SBS[1:0]
SCS[3:0]#
SCAS#
SRAS#
SWE#
SCKE[1:0]
Intel
®
82810E (GMCH)
81