NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 77

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

4.1.4.
4.2.
4.2.1.
Datasheet
R
GMCH Decode Rules and Cross-Bridge Address Mapping
Host Bus Device Support
The GMCH’s address map applies globally to accesses arriving on any of the three interfaces (i.e., Host
bus, hub interface or from the internal Graphics Device).
Hub Interface Decode Rules
The GMCH accepts all memory Read and Write accesses from hub interface to both System Memory
and Graphics Memory. Hub interface accesses that fall elsewhere within the PCI memory range will not
be accepted. The GMCH does not respond to hub interface-initiated I/O read or write cycles.
Legacy VGA Ranges
The legacy VGA memory range A0000h–BFFFFh is mapped either to the internal graphics device or to
hub interface depending on the programming of the GMS bits in the SMRAM configuration register in
GMCH Device #0, and some of the bits in the VGA registers of the internal Graphics Device. These
same bits control mapping of VGA I/O address ranges. VGA I/O range is defined as addresses where
A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases - A[15:10]
are not decoded). These bits control all accesses to the VGA ranges, including support for MDA
functionality.
I/O accesses to location 3BFh are always forwarded on to hub interface.
Host Interface
The host interface of the GMCH is optimized to support the Intel
II processor, and Intel
bus interfaces within a single device. The GMCH supports a 4-deep in-order queue (i.e., supports
pipelining of up to 4 outstanding transaction requests on the host bus) . Host bus addresses are decoded
by the GMCH for accesses to system memory, PCI memory and PCI I/O (via hub interface), PCI
configuration space and Graphics memory. The GMCH takes advantage of the pipelined addressing
capability of the processor to improve the overall system performance. The GMCH supports the 370-pin
socket and SC242 processor connectors.
The GMCH recognizes and supports a large subset of the transaction types that are defined for the Intel
Pentium III processor, Intel
However, each of these transaction types have a multitude of response types, some of which are not
supported by this controller. All transactions are processed in the order that they are received on the
processor bus.

Celeron

Pentium II processor, or Intel
TM
processor. The GMCH implements the host address, control, and data

Celeron

Pentium III processor, Intel
TM
processor bus interface.
Intel
®
82810E (GMCH)

Pentium
77
