NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 64

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
3.6.3.
64
®
82810E (GMCH)
DRAMCH—DRAM Control High
Memory Offset Address:
Default Value:
Access:
Size:
7:5
4:3
2:0
Bit
7
Reserved
DRAM Refresh Rate (DRR). DRAM refresh is controlled using this field. Disabling refresh results in the
eventual loss of DRAM data, although refresh can be briefly disabled without data loss. The field must
be set to normal refresh as soon as possible once DRAM testing is completed.
00 = Refresh Disabled
01 = Refresh Enabled (default)
10 = Reserved
11 = Reserved
Special Mode Select (SMS). These bits select special SDRAM modes used for testing and
initialization. The NOP command must be programmed first before any other command can be issued.
000 = Normal SDRAM mode (Normal, default).
001 = NOP Command Enable (NCE). This state forces cycles to DRAM to generate SDRAM NOP
010 = All Banks Precharge Command Enable (ABPCE). This state forces cycles to DRAM to
011 = Mode Register Command Enable (MRCE). This state forces all cycles to DRAM to be converted
100 = CBR Cycle Enable (CBRCE). This state forces cycles to DRAM to generate SDRAM CBR
101 = Reserved.
11X = Reserved.
Reserved
commands.
generate an all banks precharge command.
into MRS commands. The command is driven on the LMA[11:0] lines. LMA[2:0] correspond to the
burst length, LMA[3] corresponds to the wrap type, and LMA[6:4] correspond to the latency mode.
LMA[11:7] are driven to 00000 by the GMCH,
The BIOS must select an appropriate host address for each row of memory such that the right
commands are generated on the LMA[6:0] lines, taking into account the mapping of host
addresses to display cache addresses.
refresh cycles.
5
3002h
08h
Read / write
8 bit
4
DRAM Refresh Rate
Description
3
2
Special Mode Select
Datasheet
0
R