NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 3

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NH82810 S L7XK

Manufacturer Part Number
NH82810 S L7XK
Description
Manufacturer
Intel
Datasheet

Specifications of NH82810 S L7XK

Lead Free Status / RoHS Status
Compliant
Contents
1.
2.
3.
Datasheet
R
Overview.....................................................................................................................................11
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
1.7.
1.8.
1.9.
Signal Description.......................................................................................................................17
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
2.8.
2.9.
2.10.
Configuration Registers ..............................................................................................................25
3.1.
3.2.
3.3.
3.4.
The Intel
GMCH Overview ............................................................................................................13
Host Interface.................................................................................................................14
System Memory Interface ..............................................................................................14
Display Cache Interface .................................................................................................14
Hub Interface..................................................................................................................14
GMCH Graphics Support ...............................................................................................15
1.7.1.
System Clocking ............................................................................................................16
References.....................................................................................................................16
Host Interface Signals ....................................................................................................18
System Memory Interface Signals .................................................................................19
Display Cache Interface Signals ....................................................................................20
Hub Interface Signals.....................................................................................................20
Display Interface Signals................................................................................................21
Digital Video Output Signals/TV-Out Pins......................................................................22
Power Signals ................................................................................................................23
Clock Signals .................................................................................................................23
Miscellaneous Interface Signals.....................................................................................24
Power-Up/Reset Strap Options......................................................................................24
Register Nomenclature and Access Attributes ..............................................................25
PCI Configuration Space Access ...................................................................................26
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.2.5.
I/O Mapped Registers ....................................................................................................28
3.3.1.
3.3.2.
Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0)....................30
3.4.1.
3.4.2.
3.4.3.
3.4.4.
3.4.5.
3.4.6.
3.4.7.
3.4.8.
3.4.9.
3.4.10.
3.4.11.
®
810E Chipset System ....................................................................................11
Display, Digital Video Out, and LCD/Flat Panel ...........................................15
PCI Bus Configuration Mechanism ..............................................................26
Logical PCI Bus #0 Configuration Mechanism.............................................27
Primary PCI (PCI0) and Downstream Configuration Mechanism ................27
Internal Graphics Device Configuration Mechanism....................................27
GMCH Register Introduction........................................................................27
CONFIG_ADDRESSConfiguration Address Register ..............................28
CONFIG_DATAConfiguration Data Register ...........................................29
VIDVendor Identification Register (Device 0)...........................................31
DIDDevice Identification Register (Device 0) ...........................................31
PCICMDPCI Command Register (Device 0)............................................32
PCISTSPCI Status Register (Device 0) ...................................................33
RIDRevision Identification Register (Device 0) ........................................34
SUBCSub-Class Code Register (Device 0) .............................................34
BCCBase Class Code Register (Device 0) ..............................................34
MLTMaster Latency Timer Register (Device 0) .......................................35
HDRHeader Type Register (Device 0) .....................................................35
SVID    Subsystem Vendor Identification Register (Device 0)......................35
SID    Subsystem Identification Register (Device 0).....................................36
Intel
®
82810E (GMCH)
3

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