NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 58

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
3.5.16.
3.5.17.
3.5.18.
58
®
82810E (GMCH)
ROMADR    Video BIOS ROM Base Address Registers
CAPPOINT    Capabilities Pointer Register (Device 1)
SID    Subsystem Identification Register (Device 1)
Address Offset:
Default Value:
Access:
(Device 1)
Address Offset:
Default Value:
Access:
The internal graphics device of the GMCH does not use a separate BIOS ROM, therefore this is
hardwired to 0s.
Address Offset:
Default Value:
Access:
31:18
17:11
Bit
7:0
15:0
31
15
10:1
Bit
Bit
0
(HW=0; 256KB addr range)
Pointer to the Atart of AGP Register Block. Since there is no AGP bus on the GMCH, this field is set
to DCh to point to the Power Management Capabilities ID Register
Address Mask (cont)
Subsystem ID—R/WO. This value is used to identify a particular subsystem. The default value is
0000h. This field should be programmed by BIOS during boot-up. Once written, this register becomes
Read_Only. This Register can only be cleared by a Reset.
ROM Base Address    RO. Hardwired to 0s.
Address Mask    RO. Hardwired to 0s to indicate 256 KB address range.
Reserved. Hardwired to 0s.
ROM BIOS Enable    RO. 0 = ROM not accessible.
ROM Base Address
(addr bits [31:19])
11
2E−2Fh
0000h
Read/Write Once
30−33h
00000000h
Read Only
34h
DCh
Read Only
10
Descriptions
Descriptions
Descriptions
Reserved (HW=0)
18
17
Address Mask (HW=0;
256KB addr range)
1
BIOS En
(HW=0)
ROM
Datasheet
0
16
R