NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 54

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
3.5.8.
3.5.9.
3.5.10.
54
®
82810E (GMCH)
CLS    Cache Line Size Register (Device 1)
BCC1—Base Class Code Register (Device 1)
MLT    Master Latency Timer Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This register contains the Base Class Code of the GMCH Function #1.
Address Offset:
Default Value:
Access:
The internal graphics device of the GMCH does not support this register as a PCI slave.
Address Offset:
Default Value:
Access:
The internal graphics device of the GMCH does not support the programmability of the master latency
timer because it does not perform bursts.
7:0
7:0
7:0
Bit
Bit
Bit
Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the GMCH.
This code has the value 03h, indicating a display controller.
Cache Line Size (CLS). Hardwired to 0’s. The internal graphics device of the GMCH as a PCI
compliant master does not use the Memory Write and Invalidate command and, in general, does not
perform operations based on cache line size.
Master Latency Timer Count Value. Hardwired to 0s.
0Bh
03h
Read Only
8 bits
0Ch
00h
Read only
0Dh
00h
Read Only
Description
Description
Description
Datasheet
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