NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 6

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
Figures
Tables
6
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82810E (GMCH)
Figure 1. Intel
Figure 2. GMCH Block Diagram............................................................................................... 13
Figure 3. System Memory Address Map .................................................................................. 70
Figure 4. Detailed Memory System Address Map.................................................................... 71
Figure 5 GMCH’s Graphics Register Memory Address Space ................................................ 74
Figure 6. DRAM Array Sockets (2 DIMM Sockets) .................................................................. 85
Figure 7. GMCH Display Cache Interface to 4 MB................................................................... 87
Figure 8. 3D/2D Pipeline Preprocessor.................................................................................... 89
Figure 9. Data Flow for the 3D Pipeline ................................................................................... 91
Figure 10. GMCH Pinout (Top View—Left Side).................................................................... 104
Figure 11. GMCH Pinout (Top View—Right Side) ................................................................. 105
Figure 12. GMCH Package Dimensions (421 BGA) – Top and Side Views .......................... 109
Figure 13. GMCH Package Dimensions (421 BGA) – Bottom View...................................... 110
Figure 14. XOR Tree Implementation .................................................................................... 111
Table 1. Power Up Options ...................................................................................................... 24
Table 2. Host Frequency Strappings........................................................................................ 24
Table 3. GMCH PCI Configuration Space (Device 0) .............................................................. 30
Table 4. Programming DRAM Row Population Register Fields............................................... 40
Table 5. GMCH Configuration Space (Device 1) ..................................................................... 49
Table 6 Memory Mapped Registers ......................................................................................... 62
Table 7. Memory Segments and their Attributes...................................................................... 72
Table 8. Summay of Transactions Supported By GMCH......................................................... 78
Table 9. Host Responses Supported by the GMCH ................................................................ 79
Table 10. Special Cycles.......................................................................................................... 80
Table 11. Sample Of Possible Mix And Match Options For 4 Row/2 DIMM Configurations .... 82
Table 12. Data Bytes on DIMM Used for Programming DRAM Registers ............................... 83
Table 13. GMCH DRAM Address Mux Function...................................................................... 84
Table 14. Programmable SDRAM Timing Parameters ............................................................ 85
Table 15. Memory Size for Each Configuration........................................................................ 87
Table 16. Partial List of Display Modes Supported .................................................................. 97
Table 17. Partial List of Flat Panel Modes Supported .............................................................. 99
Table 18. Partial List of TV-Out Modes Supported ................................................................ 100
Table 19. Alphabetical Pin Assignment.................................................................................. 106
Table 20. GMCH Package Dimensions (421 BGA) ............................................................... 110
Table 21. XOR Test Pattern Example.................................................................................... 112
Table 22. XOR Chain 1 .......................................................................................................... 114
Table 23. XOR Chain 2 .......................................................................................................... 114
Table 24. XOR Chain 3 .......................................................................................................... 115
Table 25. XOR Chain 4 .......................................................................................................... 116
Table 26. XOR Chain 5 .......................................................................................................... 117
Table 27. XOR Chain 6 .......................................................................................................... 118
Table 28. XOR Chain 7 .......................................................................................................... 119
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810E Chipset System Block Diagram With Intel 82810E GMCH and ICH...... 12
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