NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 37

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

3.4.13.
Datasheet
R
GMCHCFGGMCH Configuration Register (Device 0)
Offset:
Default:
Access:
Size:
Bit
Reserved
7
6
5
4
3
2
1
0
7
Reserved
Processor Latency Timer (CLT).
1 = A “deferrable” processor cycle will only be Deferred after in has been held in a “Snoop Stall” for 31
0 = A “deferrable” processor cycle will be Deferred immediately after the GMCH receives another ADS#
Reserved
Local Memory Frequency Select (LMFS). This bit selects the operating frequency for the Local
Memory Controller in Whitney
1 = 133 MHz
0 = 100 MHz
This bit must be modified before enabling the internal graphics device (i.e., bits bit 7:6, Reg. 70h)
DRAM Page Closing Policy (DPCP). This bit controls whether the GMCH will precharge bank or
precharge all during the service of a page miss.
1 = The GMCH will prechange all during the service of a page miss.
0 = The GMCH will prechange bank during the service of a page miss.
Reserved
D8 Hole Enable (D8HEN).
1 = Enable. All accesses to the address range 000D8000h–000DFFFh are forwarded on to the ICH,
0 = Disable. The “D8 Hole” region is controlled by bits 3:2 of the PAM registers.
CD Hole Enable ( CDHEN ).
1 = Enable. All accesses to the address range 000DC000h–000DFFFFh are forwarded on to ICH,
0 = Disable. The “CD Hole” region is controlled by bits 3 & 2 of the PAM Register.
clocks and another ADS# has arrived.
independent of the programming of the PAM registers.
independent of the programming of the PAM register.
Processor
Latency
Timer
6
5
Reserved
50h
60h
Read/Write, Read Only
8 bits
Frequency
Memory
Select
Local
4
Description
DRAM Pg
Closing
Policy
3
Reserved
2
D8 Hole
Intel
Enable
1
®
82810E (GMCH)
CD Hole
Enable
0
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