Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 13

• Manufacturer Part Number: Z84C3006PEG
• Description: IC 6MHZ Z80 CMOS CTC 28-PDIP
• Manufacturer: Zilog
• Type: Counter/Timer Circuit (CTC)r
• Series: Z80r

Specifications of Z84C3006PEG

• Frequency: 6MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z84C3xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Filter Terminals: SMD
• Ic Generic Number: 84C30
• Operating Temperature Min: -40°C
• Operating Temperature Max: 100°C
• Clock Frequency: 6MHz
• Rohs Compliant: Yes
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3910; Z84C3006PEG

List of Figures
UM008005-0205
Figure 1. Z80 CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Figure 2. Z80 CPU Register Configuration . . . . . . . . . . . . . . . . . . . . . . .3
Figure 3. Z80 I/O Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 4. Basic CPU Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 5. Instruction Op Code Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 6. Memory Read or Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 7. Input or Output Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 8. Bus Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . .16
Figure 9. Interrupt Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . .17
Figure 10. Non-Maskable Interrupt Request Operation . . . . . . . . . . . . .18
Figure 11. HALT Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 12. Power-Down Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 13. Power-Down Release Cycle No. 1 . . . . . . . . . . . . . . . . . . . .20
Figure 14. Power-Down Release Cycle No. 2 . . . . . . . . . . . . . . . . . . . .20
Figure 15. Power-Down Release Cycle No. 3 . . . . . . . . . . . . . . . . . . . .21
Figure 16. Mode 2 Interrupt Response Mode . . . . . . . . . . . . . . . . . . . . .26
Figure 17. Minimum Z80 Computer System . . . . . . . . . . . . . . . . . . . . .28
Figure 18. ROM and RAM Implementation . . . . . . . . . . . . . . . . . . . . . .29
Figure 19. Adding One Wait State to an M1 Cycle . . . . . . . . . . . . . . . .30
Figure 20. Adding One Wait State to Any Memory Cycle . . . . . . . . . .31
Figure 21. Interfacing Dynamic RAMs . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 22. Shifting of BCD Digits/Bytes . . . . . . . . . . . . . . . . . . . . . . . .36
User’s Manual
List of Figures
Z80 CPU
xv