Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 73

IC 6MHZ Z80 CMOS CTC 28-PDIP

Z84C3006PEG

Manufacturer Part Number
Z84C3006PEG
Description
IC 6MHZ Z80 CMOS CTC 28-PDIP
Manufacturer
Zilog
Type
Counter/Timer Circuit (CTC)r
Series
Z80r
Datasheets

Specifications of Z84C3006PEG

Frequency
6MHz
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 100°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
Z84C3xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
6 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Filter Terminals
SMD
Ic Generic Number
84C30
Operating Temperature Min
-40°C
Operating Temperature Max
100°C
Clock Frequency
6MHz
Rohs Compliant
Yes
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
28
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Lead Free Status / Rohs Status
 Details
Other names
269-3910
Z84C3006PEG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z84C3006PEG
Manufacturer:
ZILOG
Quantity:
1 980
Part Number:
Z84C3006PEG
Manufacturer:
Zilog
Quantity:
1 722
Part Number:
Z84C3006PEG
Manufacturer:
ZILOG
Quantity:
1 980
Part Number:
Z84C3006PEG
Manufacturer:
WSI
Quantity:
4 970
Part Number:
Z84C3006PEG
Manufacturer:
ZILOG
Quantity:
20 000
UM008005-0205
Loading a memory location using indexed addressing for the destination
and immediate addressing for the source requires four bytes. For example,
LD (IX - 15), 21H
appears as:
Notice that with any indexed addressing the displacement always follows
directly after the Op Code.
Table 7 specifies the 16-bit load operations. The extended addressing
feature covers all register pairs. Register indirect operations specifying
the stack pointer are the
these instructions is
that the stack pointer is automatically decremented and incremented as
each byte is pushed onto or popped from the stack respectively. For
example, the instruction
Op Code of
Decrement SP
LD (SP), A
Decrement SP
LD (SP), F
The external stack now appears as:
Address A
A+1
A+2
A+3
DD
F1
36
21
F5H
Op Code
One or Two Bytes
Displacement (-15 in Signed
Two’s Complement
Operand to Load
. During execution, this sequence is generated:
PUSH
PUSH
PUSH AF
and
POP
and
. These differ from other 16-bit loads in
POP
is a single byte instruction with the
instructions. The mnemonic for
Z80 CPU Instruction Description
User’s Manual
Z80 CPU
53

Related parts for Z84C3006PEG