Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 85
![IC 6MHZ Z80 CMOS CTC 28-PDIP](/photos/6/57/65755/269-28-dip_sml.jpg)
Z84C3006PEG
Manufacturer Part Number
Z84C3006PEG
Description
IC 6MHZ Z80 CMOS CTC 28-PDIP
Manufacturer
Zilog
Type
Counter/Timer Circuit (CTC)r
Series
Z80r
Specifications of Z84C3006PEG
Frequency
6MHz
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 100°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
Z84C3xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
6 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Filter Terminals
SMD
Ic Generic Number
84C30
Operating Temperature Min
-40°C
Operating Temperature Max
100°C
Clock Frequency
6MHz
Rohs Compliant
Yes
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
28
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Lead Free Status / Rohs Status
Details
Other names
269-3910
Z84C3006PEG
Z84C3006PEG
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UM008005-0205
Three types of register indirect jumps are also included. These
instructions are implemented by loading the register pair HL or one of the
index registers 1X or IY directly into the PC. This feature allows for
program jumps to be a function of previous calculations.
A call is a special form of a jump where the address of the byte following
the call instruction is pushed onto the stack before the jump is made. A
return instruction is the reverse of a call because the data on the top of the
stack is popped directly into the PC to form a jump address. The call and
return instructions allow for simple subroutine and interrupt handling.
Two special return instruction are included in the Z80 family of
components. The return from interrupt instruction (
from nonmaskable interrupt (
unconditional return identical to the Op Code
(
peripheral chips recognize the execution of this instruction for proper
control of nested priority interrupt handling. This instruction, coupled
with the Z80 peripheral devices implementation, simplifies the normal
return from nested interrupt. Without this feature, the following software
sequence is necessary to inform the interrupting device that the interrupt
routine is completed:
This seven byte sequence can be replaced with the one byte
and the two byte
interrupt service time often must be minimized.
Table 15. Bit Manipulation Group
Disable Interrupt
LD A, n
OUT n, A
Enable Interrupt
Return
RETI
Bit
) can be used at the end of an interrupt routine and all Z80
Register Addressing
A
8
Prevent interrupt before routine is exited.
Notify peripheral that service
routine is complete.
RETI
C
instruction in the Z80. This is important because
D
RETN
E
) are treated in the CPU as an
H
Z80 CPU Instruction Description
L
C9H
. The difference is that
RETI
Reg. Indir.
(HL)
User’s Manual
) and the return
EI
Indexed
(IX+d)
DD
Z80 CPU
instruction
(IY+d)
FD
65
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