Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 28
Z84C3006PEG
Manufacturer Part Number
Z84C3006PEG
Description
IC 6MHZ Z80 CMOS CTC 28-PDIP
Manufacturer
Zilog
Type
Counter/Timer Circuit (CTC)r
Series
Z80r
Specifications of Z84C3006PEG
Frequency
6MHz
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 100°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
Z84C3xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
6 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Filter Terminals
SMD
Ic Generic Number
84C30
Operating Temperature Min
-40°C
Operating Temperature Max
100°C
Clock Frequency
6MHz
Rohs Compliant
Yes
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
28
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Lead Free Status / Rohs Status
Details
Other names
269-3910
Z84C3006PEG
Z84C3006PEG
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8
UM008005-0205
Z80 CPU
User’s Manual
BUSACK
Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the
requesting device that the CPU address bus, data bus, and control signals
MREQ, IORQ RD, and WR have entered their high-impedance states. The
external circuitry can now control these lines.
BUSREQ
Bus Request (input, active Low). Bus Request has a higher priority than
NMI and is always recognized at the end of the current machine cycle.
BUSREQ forces the CPU address bus, data bus, and control signals MREQ
IORQ, RD, and WR to go to a high-impedance state so that other devices
can control these lines. BUSREQ is normally wired-OR and requires an
external pull-up for these applications. Extended BUSREQ periods due to
extensive DMA operations can prevent the CPU from properly refreshing
dynamic RAMS.
D7–D0
Data Bus (input/output, active High, tristate). D7–D0 constitute an
8-bit bidirectional data bus, used for data exchanges with memory and I/O.
HALT
HALT State (output, active Low). HALT indicates that the CPU has
executed a HALT instruction and is waiting for either a non-maskable or a
maskable interrupt (with the mask enabled) before operation can resume.
During HALT, the CPU executes NOPs to maintain memory refresh.
INT
Interrupt Request (input, active Low). Interrupt Request is generated by
I/O devices. The CPU honors a request at the end of the current instruction if
the internal software-controlled interrupt enable flip-flop (IFF) is enabled.
INT is normally wired-OR and requires an external
pull-up for these applications.
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