Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 99

• Manufacturer Part Number: Z84C3006PEG
• Description: IC 6MHZ Z80 CMOS CTC 28-PDIP
• Manufacturer: Zilog
• Type: Counter/Timer Circuit (CTC)r
• Series: Z80r

Specifications of Z84C3006PEG

• Frequency: 6MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z84C3xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Filter Terminals: SMD
• Ic Generic Number: 84C30
• Operating Temperature Min: -40°C
• Operating Temperature Max: 100°C
• Clock Frequency: 6MHz
• Rohs Compliant: Yes
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3910; Z84C3006PEG

UM008005-0205
Byte Count Register (
decrements to
During
of the interrupt enable flip-flop (
When inputting a byte from an I/O device with an
the P/V Flag is adjusted to indicate the data parity.
Half Carry Flag
The Half-Carry Flag (H) is set (
and Borrow status between Bits 3 and 4 of an 8-bit arithmetic operation.
This flag is used by the
(
H Flag is set (
Zero Flag
The Zero Flag (Z) is set (1) or cleared (0) if the result generated by the
execution of certain instructions is 0.
For 8-bit arithmetic and logical operations, the Z flag is set to a
resulting byte in the Accumulator is
reset to
For compare (Search) instructions, the Z flag is set to
Accumulator is equal to the value in the memory location indicated by the
value of the Register pair HL.
When testing a bit in a register or memory location, the Z flag contains the
complemented state of the indicated bit (see “Bit b, s”).
H Flag Add
1
0
DAA
) to correct the result of a packed BCD add or subtract operation. The
LD A, I
0
A Carry occurs from Bit 3 to Bit 4 A Borrow from Bit 4 occurs
No Carry occurs from Bit 3 to Bit 4 No Borrow from Bit 4 occurs
.
1
0
) or cleared (
, the flag is cleared to
and
LD A, R
BC
Decimal Adjust Accumulator
). When decrementing, if the byte counter
0
instructions, the P/V Flag is set with the value
) according to the following table:
1
IFF2
) or cleared (
0
0
) for storage or testing.
. If the byte is not
, otherwise the flag is set to
Subtract
0
) depending on the Carry
IN r
1
if the value in the
Z80 Instruction Set
, (
User’s Manual
0
C
, the Z flag is
instruction
), instruction,
Z80 CPU
1
1
if the
.
79