Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 152

• Manufacturer Part Number: Z84C3006PEG
• Description: IC 6MHZ Z80 CMOS CTC 28-PDIP
• Manufacturer: Zilog
• Type: Counter/Timer Circuit (CTC)r
• Series: Z80r

Specifications of Z84C3006PEG

• Frequency: 6MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z84C3xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Filter Terminals: SMD
• Ic Generic Number: 84C30
• Operating Temperature Min: -40°C
• Operating Temperature Max: 100°C
• Clock Frequency: 6MHz
• Rohs Compliant: Yes
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3910; Z84C3006PEG

132
Operation:
Op Code:
Operands:
Description: This 2-byte instruction transfers a byte of data from the memory
Condition Bits Affected:
UM008005-0205
Z80 CPU
User’s Manual
(DE) ← (HL), DE ← D ← 1, HL ← HL-1, BC ← BC-1
LDDR
—
location addressed by the contents of the HL register pair to the memory
location addressed by the contents of the DE register pair. Then both of
these registers, as well as the BC (Byte Counter), are decremented. If
decrementing causes BC to go to zero, the instruction is terminated. If
BC is not zero, the program counter is decremented by two and the
instruction is repeated. Interrupts are recognized and two refresh cycles
execute after each data transfer.
When BC is set to zero, prior to instruction execution, the instruction loops
through 64 Kbytes.
For BC ≠ 0:
For BC = 0:
S is not affected
Z is not affected
H is reset
P/V is reset
N is reset
1
1
1
0
M Cycles
M Cycles
1
1
5
4
0
1
1
1
21 (4, 4, 3, 5, 5)
LDDR
16 (4, 4, 3, 5)
1
0
T States
T States
0
0
1
0
ED
B8
4 MHz E.T.
4 MHz E.T.
5.25
4.00
Z80 Instruction Set