Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 32
Z84C3006PEG
Manufacturer Part Number
Z84C3006PEG
Description
IC 6MHZ Z80 CMOS CTC 28-PDIP
Manufacturer
Zilog
Type
Counter/Timer Circuit (CTC)r
Series
Z80r
Specifications of Z84C3006PEG
Frequency
6MHz
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 100°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
Z84C3xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
6 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Filter Terminals
SMD
Ic Generic Number
84C30
Operating Temperature Min
-40°C
Operating Temperature Max
100°C
Clock Frequency
6MHz
Rohs Compliant
Yes
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
28
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Lead Free Status / Rohs Status
Details
Other names
269-3910
Z84C3006PEG
Z84C3006PEG
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12
UM008005-0205
Z80 CPU
User’s Manual
CLK
Instruction Fetch
T Cycle
T1
Figure 4.
Figure 5 depicts the timing during an M1 (opcode fetch) cycle. The PC is
placed on the address bus at the beginning of the M1 cycle. One half clock
cycle later the MREQ signal goes active. At this time the address to the
memory has had time to stabilize so that the falling edge of MREQ can be
used directly as a chip enable clock to dynamic memories. The RD line also
goes active to indicate that the memory read data should be enabled onto the
CPU data bus. The CPU samples the data from the memory on the data bus
with the rising edge of the clock of state T3 and this same edge is used by
the CPU to turn off the RD and MREQ signals. Thus, the data has already
been sampled by the CPU before the RD signal becomes inactive. Clock
state T3 and T4 of a fetch cycle are used to refresh dynamic memories. The
CPU uses this time to decode and execute the fetched instruction so that no
other operation could be performed at this time.
During T3 and T4, the lower seven bits of the address bus contain a memory
refresh address and the RFSH signal becomes active tindicating that a
refresh read of all dynamic memories must be accomplished. An RD signal
is not generated during refresh time to prevent data from different memory
Machine Cycle
(Opcode Fetch)
T2
M1
Basic CPU Timing Example
T3
Instruction Cycle
T1
(Memory Read)
M2
T2
T3
T1
(Memory Write)
M3
T2
T3
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