Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 54
Z84C3006PEG
Manufacturer Part Number
Z84C3006PEG
Description
IC 6MHZ Z80 CMOS CTC 28-PDIP
Manufacturer
Zilog
Type
Counter/Timer Circuit (CTC)r
Series
Z80r
Specifications of Z84C3006PEG
Frequency
6MHz
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 100°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
Z84C3xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
6 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Filter Terminals
SMD
Ic Generic Number
84C30
Operating Temperature Min
-40°C
Operating Temperature Max
100°C
Clock Frequency
6MHz
Rohs Compliant
Yes
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
28
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Lead Free Status / Rohs Status
Details
Other names
269-3910
Z84C3006PEG
Z84C3006PEG
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34
UM008005-0205
Z80 CPU
User’s Manual
Examples of Specific Z80 Instructions
After the execution of an instruction that sets a flag, that flag can be used to
control a conditional jump or return instruction. These instructions provide
logical control following the manipulation of single bit, 8-bit byte, or 18-bit
data quantities.
A full set of logical operations, including
CPL
tions between the accumulator and all other 8-bit registers, memory loca-
tions, or immediate operands.
In addition, a full set of arithmetic and logical shifts in both directions are
available which operate on the contents of all 8-bit primary registers or
directly on any memory location. The carry flag can be included or set by
these shift instructions to provide both the testing of shift results and to link
register/register or register/memory shift operations.
Example One:
When a 737-byte data string in memory location DATA must be moved to
location BUFFER, the operation is programmed as follows:
Eleven bytes are required for this operation and each byte of data is moved
in 21 clock cycles.
LD
LD
LD
LDIR
(
NOR
HL, DATA
DE, BUFFER;START ADDRESS OF TARGET BUFFER
BC, 737
), and
NEG
(two’s complement) are available for Boolean opera-
;START ADDRESS OF DATA STRING
;LENGTH OF DATA STRING
;MOVE STRING - TRANSFER MEMORY POINTED
;TO BY HL INTO MEMORY LOCATION POINTED
;TO BY DE INCREMENT HL AND DE,
;DECREMENT BC PROCESS UNTIL BC = 0.
Hardware and Software Implementation Examples
AND
,
OR
,
XOR
(exclusive-
OR
),
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