Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 158

• Manufacturer Part Number: Z84C3006PEG
• Description: IC 6MHZ Z80 CMOS CTC 28-PDIP
• Manufacturer: Zilog
• Type: Counter/Timer Circuit (CTC)r
• Series: Z80r

Specifications of Z84C3006PEG

• Frequency: 6MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z84C3xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Filter Terminals: SMD
• Ic Generic Number: 84C30
• Operating Temperature Min: -40°C
• Operating Temperature Max: 100°C
• Clock Frequency: 6MHz
• Rohs Compliant: Yes
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3910; Z84C3006PEG

138
Operation:
Op Code:
Operands:
Description: The contents of the memory location addressed by the HL register pair is
Condition Bits Affected:
UM008005-0205
Z80 CPU
User’s Manual
A -(HL), HL ← HL -1, BC ← BC -1
CPDR
—
compared with the contents of the Accumulator. In case of a true compare,
a condition bit is set. The HL and BC (Byte Counter) register pairs are
decremented. If decrementing causes the BC to go to zero or if A = (HL),
the instruction is terminated. If BC is not zero and A = (HL), the program
counter is decremented by two and the instruction is repeated. Interrupts are
recognized and two refresh cycles execute after each data transfer. When
BC is set to zero, prior to instruction execution, the instruction loops
through 64 Kbytes if no match is found.
For BC ≠ 0 and A ≠ (HL):
For BC = 0 and A = (HL):
S is set if result is negative; reset otherwise
Z is set if A = (HL); reset otherwise
H is set if borrow form bit 4; reset otherwise
P/V is set if BC -1 ≠ 0; reset otherwise
N is set
C is not affected
1
1
1
0
M Cycles
M Cycles
1
1
5
4
0
1
1
1
21 (4, 4, 3, 5, 5)
CPDR
16 (4, 4, 3, 5)
1
0
T States
T States
0
0
1
1
ED
B9
4 MHz E.T.
4 MHz E.T.
5.25
4.00
Z80 Instruction Set