Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 285

• Manufacturer Part Number: Z84C3006PEG
• Description: IC 6MHZ Z80 CMOS CTC 28-PDIP
• Manufacturer: Zilog
• Type: Counter/Timer Circuit (CTC)r
• Series: Z80r

Specifications of Z84C3006PEG

• Frequency: 6MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z84C3xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Filter Terminals: SMD
• Ic Generic Number: 84C30
• Operating Temperature Min: -40°C
• Operating Temperature Max: 100°C
• Clock Frequency: 6MHz
• Rohs Compliant: Yes
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3910; Z84C3006PEG

Operation:
Op Code:
Description: This instruction is used at the end of a non-maskable interrupts service
Condition Bits Affected: None
Example:
UM008005-0205
Return from non maskable interrupt
RETN
routine to restore the contents of the Program Counter (PC) (analogous to
the RET instruction). The state of IFF2 is copied back to IFF1 so that
maskable interrupts are enabled immediately following the RETN if they
were enabled before the nonmaskable interrupt.
If the contents of the Stack Pointer are
Program Counter are
is received, the CPU ignores the next instruction and instead restarts to
memory address
is pushed onto the external stack address of
byte first, and
begins an interrupt service routine that ends with a
Upon the execution of
popped off the external memory stack, low order first, resulting in a Stack
Pointer contents again of
left off with an Op Code fetch to address
0066H is loaded onto the Program Counter. That address begins an
interrupt service routine that ends with a
RETN
memory stack, low order first, resulting in a Stack Pointer contents again of
1
0
the former Program Counter contents are popped off the external
1
1
M Cycles
1
0
4
0066H
0
0
0066H
1A45H
1
0
is loaded onto the Program Counter. That address
. The current Program Counter contents of
RETN
RETN
1000H
14 (4, 4, 3, 3)
1
1
T States
, when a non maskable interrupt (NMI) signal
the former Program Counter contents are
0
0
. The program flow continues where it
1
1
1000H
RETN
ED
45
1A45H
0FFFH
, and the contents of the
4 MHz E.T.
instruction. At execution of
, order-byte first, and
3.50
and
RETN
0FFEH
Z80 Instruction Set
User’s Manual
instruction.
, high order-
Z80 CPU
1A45H
265