Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 30
![IC 6MHZ Z80 CMOS CTC 28-PDIP](/photos/6/57/65755/269-28-dip_sml.jpg)
Z84C3006PEG
Manufacturer Part Number
Z84C3006PEG
Description
IC 6MHZ Z80 CMOS CTC 28-PDIP
Manufacturer
Zilog
Type
Counter/Timer Circuit (CTC)r
Series
Z80r
Specifications of Z84C3006PEG
Frequency
6MHz
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 100°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
Z84C3xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
6 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Filter Terminals
SMD
Ic Generic Number
84C30
Operating Temperature Min
-40°C
Operating Temperature Max
100°C
Clock Frequency
6MHz
Rohs Compliant
Yes
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
28
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Lead Free Status / Rohs Status
Details
Other names
269-3910
Z84C3006PEG
Z84C3006PEG
Available stocks
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Manufacturer
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Price
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Z84C3006PEG
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ZILOG
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1 980
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10
UM008005-0205
Z80 CPU
User’s Manual
interrupt status to Mode 0. During reset time, the address and data bus go to
a high-impedance state, and all control output signals go to the inactive
state. Notice that RESET must be active for a minimum of three full clock
cycles before the reset operation is complete.
RFSH
Refresh (output, active Low). RFSH, together with MREQ indicates that
the lower seven bits of the system’s address bus can be used as a refresh
address to the system’s dynamic memories.
WAIT
WAIT (input, active Low). WAIT communicates to the CPU that the
addressed memory or I/O devices are not ready for a data transfer. The CPU
continues to enter a WAIT state as long as this signal is active. Extended
WAIT periods can prevent the CPU from properly refreshing dynamic
memory.
WR
Write (output, active Low, tristate). WR indicates that the CPU data bus
holds valid data to be stored at the addressed memory or I/O location.
CLK
Clock (input). Single-phase MOS-level clock.
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