Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 80

• Manufacturer Part Number: Z84C3006PEG
• Description: IC 6MHZ Z80 CMOS CTC 28-PDIP
• Manufacturer: Zilog
• Type: Counter/Timer Circuit (CTC)r
• Series: Z80r

Specifications of Z84C3006PEG

• Frequency: 6MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z84C3xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Filter Terminals: SMD
• Ic Generic Number: 84C30
• Operating Temperature Min: -40°C
• Operating Temperature Max: 100°C
• Clock Frequency: 6MHz
• Rohs Compliant: Yes
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3910; Z84C3006PEG

60
UM008005-0205
Z80 CPU
User’s Manual
Five general-purpose arithmetic instructions operate on the accumulator
or carry flag. These five are listed in Table 12. The decimal adjust
instruction can adjust for subtraction as well as addition, making BCD
arithmetic operations simple. Note that to allow for this operation the flag
N is used. This flag is set if the last arithmetic operation was a subtract.
The negate accumulator (
the number in the accumulator. Finally, notice that a reset carry
instruction is not included in the Z80 because this operation can be easily
achieved through other instructions such as a logical AND of the
accumulator with itself.
Table 13 lists all the 16-bit arithmetic operations between 16-bit registers.
There are five groups of instructions including add with carry and subtract
with carry.
address calculation operations or other 16-bit arithmetic operations.
Table 11. 8-Bit Arithmetic and Logic
ADD
ADD W CARRY
ADC
SUBTRACT
SUB
SUB w CARR
SBC
AND
XOR
ADC
Source
A
87
8F
97
9F
A7 A0 A1 A2 A3 A4 A5 A6
AF A8 A9 AA AB AC AD AE
Register Addressing
and
B
80
88
90
98
SBC
81
89
91
99
C
affect all the flags. These two groups simplify
D
82
8A 8B
92
9A 9B
NEG
E
83
93
) instruction forms the two’s complement of
F
84
8C
94
9C
L
85
8D 8E
95
9D 9E
Reg Indir.
(HL)
88
96
Z80 CPU Instruction Description
Indexed
(IX+d)
DD
86
d
DD
8E
d
DD
96
d
DD
9E
d
DD
A6
d
DD
AE
d
(lY+d)
FD
86
d
FD
8E
d
FD
96
d
FD
9E
d
FD
A6
d
FD
AE
d
Immed.
n
C6
n
CE
n
D6
n
DE
n
E6
n
EE
n