Z84C3006PEG Zilog, Z84C3006PEG Datasheet - Page 303

• Manufacturer Part Number: Z84C3006PEG
• Description: IC 6MHZ Z80 CMOS CTC 28-PDIP
• Manufacturer: Zilog
• Type: Counter/Timer Circuit (CTC)r
• Series: Z80r

Specifications of Z84C3006PEG

• Frequency: 6MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z84C3xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 6 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Filter Terminals: SMD
• Ic Generic Number: 84C30
• Operating Temperature Min: -40°C
• Operating Temperature Max: 100°C
• Clock Frequency: 6MHz
• Rohs Compliant: Yes
• Cpu Speed: 6MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 28
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3910; Z84C3006PEG

Operation:
Op Code:
Description: The contents of the HL register pair are placed on the address bus to select
Condition Bits Affected:
UM008005-0205
(C) ← (HL), B ← B -1, HL ← HL + 1
OTIR
a location in memory. The byte contained in this memory location is tempo-
rarily stored in the CPU. Then, after the byte counter (B) is decremented, the
contents of register C are placed on the bottom half (A0 through A7) of the
address bus to select the I/O device at one of 256 possible ports. Register B
may be used as a byte counter, and its decremented value is placed on the top
half (A8 through A15) of the address bus at this time. Next, the byte to be
output is placed on the data bus and written to the selected peripheral device.
Then register pair HL is incremented. If the decremented B register is not
zero, the Program Counter (PC) is decremented by two and the instruction is
repeated. If B has gone to zero, the instruction is terminated. Interrupts are
recognized and two refresh cycles are executed after each data transfer.
If B ≠ 0:
If B = 0:
1
1
1
0
Note: When B is set to zero prior to instruction execution, the instruc-
tion outputs 256 bytes of data.
M Cycles
M Cycles
1
1
5
4
0
1
1
0
21 (4, 5, 3, 4, 5)
OTIR
16 (4, 5, 3, 4)
1
0
T States
T States
0
1
1
1
ED
B3
4 MHz E.T.
4 MHz E.T.
5.25
4.00
Z80 Instruction Set
User’s Manual
Z80 CPU
283