LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 123

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
6.4.2
31-16
BITS
15-0
Reserved
Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of
the LAN9118 device. The content of this field is undefined until loaded from the EEPROM at power-
on. The host can update the contents of this field after the initialization process has completed.
ADDRH—MAC Address High Register
The MAC Address High register contains the upper 16-bits of the physical address of the
MAC. The contents of this register are optionally loaded from the EEPROM at power-on
through the EEPROM Controller if a programmed EEPROM is detected. The least significant
byte of this register (bits [7:0]) is loaded from address 0x05 of the EEPROM. The second
byte (bits [15:8]) is loaded from address 0x06 of the EEPROM. Please refer to section 5.6
for more information on the EEPROM. Section
and ADDRH registers with respect to the reception of the Ethernet physical address.
Offset:
Default Value:
2
0000FFFFh
DATASHEET
123
DESCRIPTION
Attribute:
Size:
6.4.3
details the byte ordering of the ADDRL
R/W
32 bits
Revision 1.0 (03-17-05)