LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 92

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
6.3.7
31:30
29-28
27-16
14-13
BITS
12-8
7-0
15
RX End Alignment. This field specifies the alignment that must be
maintained on the last data transfer of a buffer. The LAN9118 will add
extra DWORDs of data up to the alignment specified in the table below.
The host is responsible for removing these extra DWORDs. This
mechanism can be used to maintain cache line alignment on host
processors.
Please refer to the table
Note:
Reserved
RX DMA Count (RX_DMA_CNT). This 12-bit field indicates the amount
of data, in DWORDS, to be transferred out of the RX data FIFO before
asserting the RXD_INT. After being set, this field is decremented for
each DWORD of data that is read from the RX data FIFO. This field
can be overwritten with a new value before it reaches zero.
Force RX Discard (RX_DUMP). This self-clearing bit clears the RX
data and status FIFOs of all pending data. When a ‘1’ is written, the RX
data and status pointers are cleared to zero.
Note:
Reserved
RX Data Offset (RXDOFF). This field controls the offset value, in bytes,
that is added to the beginning of an RX data packet. The start of the
valid data will be shifted by the number of bytes specified in this field.
An offset of 0-31 bytes is a valid number of offset bytes.
Note:
Reserved
RX_CFG—Receive Configuration Register
This register controls the LAN9118 receive engine.
Offset:
The desired RX End Alignment must be set before reading a
packet. The RX end alignment can be changed between
reading receive packets, but must not be changed if the packet
is partially read.
Please refer to section “Force Receiver Discard (Receiver
Dump)” on page 67 for a detailed description regarding the
use of RX_DUMP.
The two LSBs of this field (D[9:8]) must not be modified while
the RX is running. The receiver must be halted, and all data
purged before these two bits can be modified. The upper three
bits (DWORD offset) may be modified while the receiver is
running. Modifications to the upper bits will take affect on the
next DWORD read.
Table 6.2
DESCRIPTION
6Ch
for bit definitions
DATASHEET
92
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Size:
32 bits
TYPE
R/W
R/W
R/W
RO
RO
RO
SC
DEFAULT
SMSC LAN9118
00000
000h
00b
0
-
-
-
Datasheet