LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 18

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
53,56-59,62-
71,73,75,84,
SPEED_SEL
21-26,29-
43-46,49-
33,36-40
PIN NO.
12-18
90,91
64
92
93
94
72
74
76
0
1
Host Data High
Host Data Low
Host Address
Read Strobe
Write Strobe
FIFO Select
Chip Select
Reserved
Interrupt
Request
Selector
10/100
NAME
100MBPS
10MBPS
SPEED
Table 2.1 Host Bus Interface Signals
SPEED_SEL
Table 2.2 Default Ethernet Settings
FIFO_SEL
SYMBOL
Reserved
D[31:16]
D[15:0]
A[7:1]
nWR
nRD
nCS
IRQ
DATASHEET
DEFAULT ETHERNET SETTINGS
HALF-DUPLEX
HALF-DUPLEX
I/O8 (PD)
BUFFER
O8/OD8
DUPLEX
TYPE
I (PU)
I/O8
18
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
IS
IS
IS
IS
IS
PINS
16
16
#
7
1
1
5
1
1
1
1
Bi-directional data port. Supports
Big/Little Endian Byte ordering.
Note that Pull-down’s are disabled in
32 bit mode.
Bi-directional data port. Supports
Big/Little Endian Byte ordering.
7-bit Address Port. Used to select
Internal CSR’s and TX and RX FIFOs.
Active low strobe to indicate a read
cycle.
Active low strobe to indicate a write
cycle. This signal, qualified with nCS, is
also used to wakeup the LAN9118
when it is in a reduced power state.
Active low signal used to qualify read
and write operations. This signal
qualified with nWR is also used to
wakeup the LAN9118 when it is in a
reduced power state.
Programmable Interrupt request.
Programmable polarity, source and
buffer types.
No Connect
This signal functions as a configuration
input on power-up and is used to select
the default Ethernet settings. Upon
deassertion of reset, the value of the
input is latched. This signal functions
as shown in
Ethernet
When driven high all accesses to the
LAN9118 are to the RX or TX Data
FIFOs. In this mode, the A[7:3] upper
address inputs are ignored.
Settings", below.
DESCRIPTION
Table 2.2, "Default
AUTO NEG.
DISABLED
ENABLED
SMSC LAN9118
Datasheet