LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 155

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
7.4
SYMBOL
t
t
t
t
cycle
t
t
t
csdv
t
t
csh
asu
don
doff
doh
csl
ah
FIFO_SEL
nCS, nRD
A[2:1]
Data Bus
In this mode the upper address inputs are not decoded, and any read of the LAN9118 will read the
RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is
normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9118. Timing is
identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit Direct PIO Read cycles is identical with the exception that D[31:16] is not
driven during a 16-bit read. Note that address lines A[2:1] are still used, and address bits A[7:3] are
ignored.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
RX Data FIFO Direct PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
Figure 7.3 RX Data FIFO Direct PIO Read Cycle Timing
Table 7.5 RX Data FIFO Direct PIO Read Timing
DATASHEET
155
MIN
45
32
13
0
0
0
0
TYP
Revision 1.0 (03-17-05)
MAX
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns