LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 158

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
SYMBOL
t
doh
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
DESCRIPTION
Data Output Hold Time
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
Table 7.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
DATASHEET
158
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
0
TYP
MAX
SMSC LAN9118
Datasheet
UNITS
ns