LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 160

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
7.7
SYMBOL
t
cycle
t
t
t
t
t
t
csh
asu
dsu
csl
ah
dh
FIFO_SEL
nCS, nRD
Data Bus
In this mode the upper address inputs are not decoded, and any write to the LAN9118 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9118. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit cycles is identical with the exception that D[31:16] is ignored during a 16-
bit write. Note that address lines A[2:1] are still used when the LAN9118 is operating in 32-bit and 16-
bit mode. Address bits A[7:3] are ignored.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
TX Data FIFO Direct PIO Writes
A[2:1]
DESCRIPTION
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
Figure 7.6 TX Data FIFO Direct PIO Write Timing
Table 7.8 TX Data FIFO Direct PIO Write Timing
DATASHEET
160
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
45
32
13
0
7
0
0
TYP
MAX
SMSC LAN9118
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns