LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 124

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
6.4.3
BITS
31-0
Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the
LAN9118 device. The content of this field is undefined until loaded from the EEPROM at power-on.
The host can update the contents of this field after the initialization process has completed.
ADDRL—MAC Address Low Register
The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM
Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])
is loaded from address 0x01 of the EEPROM. The most significant byte of this register is loaded from
address 0x04 of the EEPROM. Please refer to section 5.6 for more information on the EEPROM.
Table
reception of the Ethernet physical address. Also shown is the correlation between the EEPROM
addresses and ADDRL and ADDRH registers.
As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and
ADDRH registers would be programmed as shown in
load this configuration from the EEPROM are also shown.
Offset:
Default Value:
6.7below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the
ADDRESS
EEPROM
Table 6.7 ADDRL, ADDRH and EEPROM Byte Ordering
0x01
0x02
0x03
0x04
0x05
0x06
ADDRL[23:16]
ADDRL[31:24]
3
FFFFFFFFh
ADDRH[15:8]
ADDRL[15:8]
ADDRH[7:0]
ADDRL[7:0]
ADDRN
DATASHEET
124
DESCRIPTION
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Attribute:
Size:
RECEPTION ON
Figure
ORDER OF
ETHERNET
2
3
4
5
6
1
nd
6.2. The values required to automatically
st
rd
th
th
th
R/W
32 bits
SMSC LAN9118
Datasheet