LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 34

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
Reserved
Filter 3 Offset
FIELD
FIELD
30:0
The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether
or not this is a wake-up frame.
The Filter i command register controls Filter i operation.
The Filter i Offset register defines the offset in the frame’s destination address field from which the
frames are examined by Filter i.
2:1
31
3
0
Command
Filter 3
Filter 1 CRC-16
Filter 3 CRC-16
DESCRIPTION
Must be zero (0)
Byte Mask: If bit j of the byte mask is set, the CRC machine processes byte
number pattern - (offset + j) of the incoming frame. Otherwise, byte pattern -
(offset + j) is ignored.
DESCRIPTION
Address Type: Defines the destination address type of the pattern. When bit is
set, the pattern applies
only to multicast frames. When bit is cleared, the pattern applies only to unicast
frames.
RESERVED
Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled.
Table 4.2 Wake-Up Frame Filter Register Structure
Reserved
Table 4.3 Filter i Byte Mask bit definitions
Table 4.4 Filter i command bit definitions
Filter 2 Offset
FILTER I BYTE MASK DESCRIPTION
Command
Table
FILTER I COMMANDS
Table 4.5
Filter 2
Filter 0 Byte Mask
Filter 1 Byte Mask
Filter 2 Byte Mask
Filter 3 Byte Mask
DATASHEET
4.3, describes the byte mask’s bit fields.
34
describes the Filter i Offset bit fields.
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Reserved
Filter 1Offset
Table 4.4
Command
Filter 1
Filter 0 CRC-16
Filter 2 CRC-16
shows the Filter I command register.
Reserved
Filter 0 Offset
SMSC LAN9118
Command
Filter 0
Datasheet