LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 41

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9118
will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set.
The figure below illustrates the host accesses required to perform an EEPROM Read or Write
operation.
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
Busy Bit = 0
EEPROM Write
Figure 4.3 EEPROM access flow diagram
Write Data
Command
Command
Register
Register
Register
Write
Read
Idle
DATASHEET
41
EEPROM Read
Read Data
Command
Command
Register
Register
Register
Write
Read
Idle
Busy Bit = 0
Revision 1.0 (03-17-05)