LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 159

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
7.6
SYMBOL
t
cycle
t
t
t
t
t
t
csh
asu
dsu
csl
ah
dh
nCS, nRD
Data Bus
A[7:1]
PIO writes are used for all LAN9118 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are
identical with the exception that D[31:16] are ignored during a 16-bit write.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
nCS, nWR Assertion Time
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Figure 7.5 PIO Write Cycle Timing
Table 7.7 PIO Write Cycle Timing
DATASHEET
159
MIN
45
32
13
0
7
0
0
TYP
Revision 1.0 (03-17-05)
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns