MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 135
![PROCESSOR MODULE FLASH MOD5272](/photos/6/75/67555/mod5272-100ir_sml.jpg)
MOD5272-100IR
Manufacturer Part Number
MOD5272-100IR
Description
PROCESSOR MODULE FLASH MOD5272
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(2 pages)
2.MOD5272-100IR.pdf
(3 pages)
3.MOD5272-100IR.pdf
(550 pages)
Specifications of MOD5272-100IR
Module/board Type
Processor Module
Ethernet Connection Type
10/100 Ethernet Port RJ-45
Operating Voltage
3.3 V
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
MOD5272
For Use With
528-1001 - KIT DEVELOP NETWORK FOR MOD5272
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
528-1008
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MOTOROLA
when TDR is configured appropriately. PBR bits are masked by setting corresponding
PBMR bits. Results are compared with the processor’s program counter register, as defined
in TDR. Figure 5-9 shows the PC breakpoint register.
Table 5-12 describes PBR fields.
Figure 5-9 shows PBMR.
Table 5-13 describes PBMR fields.
5.4.7 Trigger Definition Register (TDR)
The TDR, shown in Table 5-11, configures the operation of the hardware breakpoint logic
that corresponds with the ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers
within the debug module. The TDR controls the actions taken under the defined conditions.
Breakpoint logic may be configured as a one- or two-level trigger. TDR[31–16] define the
second-level trigger and bits 15–0 define the first-level trigger.
DRc[4–0]
31–0
31–0 Address PC breakpoint address. The 32-bit address to be compared with the PC as a breakpoint trigger.
Bits
Bits
DRc[4–0]
Reset
Field
R/W Write. PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through
Reset
Field
R/W
Name
Mask
Name
the BDM port using the
Set Descriptions.”
31
Figure 5-10. Program Counter Breakpoint Mask Register (PBMR)
31
Write. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG
the appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.
PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to
Figure 5-9. Program Counter Breakpoint Register (PBR)
Table 5-13. PBMR Field Descriptions
instruction and via the BDM port using the wdmreg command.
RDMREG
Table 5-12. PBR Field Descriptions
and
Chapter 5. Debug Support
WDMREG
Program Counter
commands using values shown in Section 5.5.3.3, “Command
Description
Description
Mask
0x08
0x09
—
—
Programming Model
5-13
0
0
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