MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 377

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
16.3.15 UART Fractional Precision Divider Control
The UFPDn registers allow greater accuracy when deriving a transmitter/receiver clock
source from CLKIN. The use of the UFPDn registers is optional; if the contents are left in
the reset state, code written for other ColdFire devices containing UART modules will not
be affected by the addition of these registers. The contents of these registers allow the
frequency to be divided by a factor of up to 16. When autobaud is used, these registers are
updated automatically to reflect the clock rate being used. Host software can write to these
registers to make fine adjustments to the clock rate. See Section 16.5.1.2, “Calculating
Baud Rates,” for an example of UFPDn programming.
Table 16-12 describes UFPDn fields.
Address
Bits
Bits
7–6
4–0
7–4
3–0
5
Reset
Field
R/W
Figure 16-18. UART Fractional Precision Divider Control Registers (UFPDn)
Name
Name
FULL
RXS
RXB
FD
Registers (UFPDn)
—
7
Receiver status. When written to, these bits control the meaning of UISRn[RxFIFO].
00 Inhibit receiver FIFO status indication in UISRn.
01 Receiver FIFO ≥ 25% full
10 Receiver FIFO ≥ 50% full
11 Receiver FIFO ≥ 75% full
When read, these bits indicate the emptiness level of the FIFO.
00 Receiver FIFO < 25% full
01 Receiver FIFO ≥ 25% full
10 Receiver FIFO ≥ 50% full
11 Receiver FIFO ≥ 75% full
Receiver FIFO full.
0 Receiver FIFO is not full and can be loaded with a character.
1 Receiver FIFO is full. Characters loaded from the receiver when the FIFO is full are lost.
This bit is identical to USRn[FFULL].
Receiver buffer data level. Indicates the number of bytes, between 0 and 24, stored in the receiver
FIFO.
Reserved, should be cleared.
Fractional divider. The value of these bits, from 0 to 15, determine the scale factor by which the
clocking source for the transmitter and/or receiver is scaled.
Table 16-12. UFPDn Field Descriptions
Table 16-11. URFn Field Descriptions
—
Chapter 16. UART Modules
MBAR + 0x130 (UFPD0), 0x170 (UFPD1)
4
0000_0000
Description
Description
R/W
3
FD
Register Descriptions
0
16-17