MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 374

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

Register Descriptions
Table 16-9 describes UISRn and UIMRn fields.
16.3.11 UART Divider Upper/Lower Registers (UDUn/UDLn)
The UDUn registers (formerly called UBG1n) hold the MSB, and the UDLn registers
(formerly UBG2n) hold the LSB of the preload value. UDUn and UDLn concatenate to
provide a divider to CLKIN for transmitter/receiver operation, as described in
Section 16.5.1.2.1, “CLKIN Baud Rates.”
16-14
Bits
Address
7
6
5
4
3
2
1
0
Reset
Field
R/W
RxFIFO Receiver FIFO status. Once set, this bit is cleared by reading URBn.
TxFIFO
FFULL/
RxRDY
RxFTO
TxRDY
Name
COS
ABC
DB
7
Change-of-state.
0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on CTS and was programmed in UACRn[IEC] to cause an interrupt.
Autobaud calculation.
0 Autobaud is disabled or is waiting for the first receiver character.
1 The baud rate has been calculated and loaded into the clock source divider (UDUn and UDLn).
Once set, this bit is cleared by writing to UCRn[ENAB].
0 FIFO status indication is disabled or the receiver status has not changed.
1 The receiver status has changed as programmed in URFn[RXS].
Transmitter FIFO status. Once set, this bit is cleared by reading UTBn.
0 FIFO status indication is disabled or the transmitter status has not changed.
1 The transmitter status has changed as programmed in UTFn[TXS].
Receiver FIFO timeout.
0 No receiver FIFO timeout. This bit is cleared by reading all remaining data in the receiver FIFO, by
1 The receiver FIFO has timed out at 64 baud with unread data below the FIFO fullness level.
Delta break.
0 No new break-change condition to report. Section 16.3.5, “UART Command Registers (UCRn),”
1 The receiver detected the beginning or end of a received break.
RxRDY (receiver ready) if UMR1n[FFULL/RxRDY] = 0; FIFO full (FFULL) if UMR1n[FFULL/RxRDY]
= 1. Duplicate of USRn[FFULL/RxRDY].
Transmitter ready. This bit is the duplication of USRn[TxRDY].
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters
1 The transmitter holding register is empty and ready to be loaded with a character.
receiving another character into the FIFO, or if the receiver is disabled. The count to timeout is
restarted when RxFTO is cleared.
describes the
loaded into the transmitter holding register when TxRDY = 0 are not sent.
Figure 16-12. UART Divider Upper Registers (UDUn)
Table 16-9. UISRn/UIMRn Field Descriptions
RESET BREAK
MBAR + 0x118 (UDU0), 0x158 (UDU1)
MCF5272 User’s Manual
-
CHANGE INTERRUPT
Divider MSB
0000_0000
Write only
Description
command.
MOTOROLA
0