MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 84
MOD5272-100IR
Manufacturer Part Number
MOD5272-100IR
Description
PROCESSOR MODULE FLASH MOD5272
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(2 pages)
2.MOD5272-100IR.pdf
(3 pages)
3.MOD5272-100IR.pdf
(550 pages)
Specifications of MOD5272-100IR
Module/board Type
Processor Module
Ethernet Connection Type
10/100 Ethernet Port RJ-45
Operating Voltage
3.3 V
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
MOD5272
For Use With
528-1001 - KIT DEVELOP NETWORK FOR MOD5272
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
528-1008
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ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL
ASR
Bcc
BCHG
BCLR
BRA
BSET
BSR
BTST
CLR
CMP
Instruction
Instruction Set Summary
2.6.1 Instruction Set Summary
Table 2-7 lists implemented user-mode instructions by opcode.
2-16
Instruction
C
N
V
X
Z
Dy,<ea>x
<ea>y,Dx
<ea>y,Ax
#<data>,Dx
#<data>,<ea>x
Dy,Dx
Dy,<ea>x
<ea>y,Dx
#<data>,Dx
Dy,Dx
#<data>,Dx
Dy,Dx
#<data>,Dx
<label>
Dy,<ea>x
#<data>,<ea-1>x
Dy,<ea>x
#<data>,<ea-1>x
<label>
Dy,<ea>x
#<data>,<ea-1>x
<label>
Dy,<ea>x
#<data>,<ea-1>x
<ea>y,Dx
<ea>y,Ax
Operand Syntax
Carry
Negative
Overflow
Extend
Zero
Table 2-6. Notational Conventions (Continued)
Table 2-7. User-Mode Instruction Set Summary
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.B,.W
.B,.L
.B,.L
.B,.L
.B,.L
.B,.W
.B,.L
.B,.L
.B,.W
.B,.L
.B,.L
.B,.W,.L
.L
Operand Size
Condition Code Register Bit Names
MCF5272 User’s Manual
Operand Syntax
Source + destination → destination
Source + destination → destination
Immediate data + destination → destination
Immediate data + destination → destination
Source + destination + X → destination
Source & destination → destination
Immediate data & destination → destination
X/C ← (Dx << Dy) ← 0
X/C ← (Dx << #<data>) ← 0
MSB → (Dx >> Dy) → X/C
MSB → (Dx >> #<data>) → X/C
If condition true, then PC + 2 + d
~(<bit number> of destination) → Z,
Bit of destination
~(<bit number> of destination) → Z;
0 → bit of destination
PC + 2 + d
~(<bit number> of destination) → Z;
1→ bit of destination
SP – 4 → SP; next sequential PC→ (SP); PC + 2 + d
~(<bit number> of destination) → Z
0 → destination
Destination – source
n
→ PC
Operation
n
→ PC
MOTOROLA
n
→ PC
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