MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 234

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

1
FEC Frame Transmission
11.4.8.1 Transmission Errors
Transmission errors are defined in Table 11-4.
11.4.8.2 Reception Errors
Table 11-5 describes reception errors.
(Dribbling Bits)
11-10
Frame Length
Retransmission
Overrun Error The FEC maintains an internal FIFO for receiving data. If a receiver FIFO overrun occurs, the FEC
Late Collision
Attempts Limit
Carrier Sense
Transmission
The definition of what constitutes a late collision is hard-wired in the FEC.
Non-Octet
CRC Error
Transmitter
Lost during
Violation
Heartbeat
Underrun
Expired
Error
Error
Frame
Error
1
closes the buffer and sets RxBD[OV].
The FEC handles up to seven dribbling bits when the receive frame terminates non-octet aligned and
it checks the CRC of the frame on the last octet boundary. If there is a CRC error, the frame non-octet
aligned (NO) error is reported in the RxBD. If there is no CRC error, no error is reported.
When a CRC error occurs with no dribbling bits, the FEC closes the buffer and sets RxBD[CR]. CRC
checking cannot be disabled, but the CRC error can be ignored if checking is not required.
When the receive frame length exceeds R_HASH[MAX_FRAME_LENGTH], EIR[BABR] is set
indicating babbling receive error, and the LG bit in the end of frame RxBD is set.
Note: Receive frames exceeding 2047 bytes are truncated.
The FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for
that frame are then flushed and closed, with the UN bit set in the last TxBD for that frame. The FEC
continues to the next TxBD and begins transmitting the next frame.
When this error occurs and no collision is detected in the frame, the FEC sets the CSL bit in the last
TxBD for this frame. The frame is sent normally. No retries are performed as a result of this error.
The CSL bit is not set if TCR[FDEN] = 1, regardless of the state of CRS.
When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are
then flushed and closed, with the RL bit set in the last TxBD for that frame. The FEC then continues
to the next TxBD and begins sending the next frame.
The FEC stops sending. All remaining buffers for that frame are then flushed and closed, with the
LC bit set in the last TxBD for that frame. The FEC then continues to the next TxBD and begins
sending the next frame.
Some transceivers have a self-test feature called heartbeat or signal-quality error. To signify a good
self-test, the transceiver indicates a collision within 20 clocks after the FEC sends a frame. This
heartbeat condition does not imply a real collision, but that the transceiver seems to be functioning
properly.
If TCR[HBC] is set and the heartbeat condition is not detected by the FEC after a frame
transmission, then a heartbeat error occurs. When this error occurs, the FEC closes the buffer, sets
the HB bit in the Tx BD, and generates the HBERR interrupt if it is enabled.
Table 11-4. Transmission Errors
Table 11-5. Reception Errors
MCF5272 User’s Manual
Description
Description
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