MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 323
![PROCESSOR MODULE FLASH MOD5272](/photos/6/75/67555/mod5272-100ir_sml.jpg)
MOD5272-100IR
Manufacturer Part Number
MOD5272-100IR
Description
PROCESSOR MODULE FLASH MOD5272
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(2 pages)
2.MOD5272-100IR.pdf
(3 pages)
3.MOD5272-100IR.pdf
(550 pages)
Specifications of MOD5272-100IR
Module/board Type
Processor Module
Ethernet Connection Type
10/100 Ethernet Port RJ-45
Operating Voltage
3.3 V
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
MOD5272
For Use With
528-1001 - KIT DEVELOP NETWORK FOR MOD5272
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
528-1008
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MOTOROLA
13.5.15 GCI Monitor Channel Transmit Status Register
All bits in this register are read only and are cleared on hardware or software reset.
The PGMTS register contains the monitor channel status bits for each of the four transmit
ports on the MCF5272.
Bits Name
3–0
Bits Name
7
6
5
4
7
6
5
4
3
2
ACK3 Acknowledge, port 3.
ACK2 Acknowledge, port 2. See ACK3.
ACK1 Acknowledge, port 1. See ACK3.
ACK0 Acknowledge, port 0. See ACK3.
AR3
AR2
AR1
AR0
AB3
AB2
—
Figure 13-27. GCI Monitor Channel Transmit Status Register (PGMTS)
(PGMTS)
Abort request, port 3.
0 Default reset value.
1 Set by the CPU, this bit causes the monitor channel controller to transmit the end of message signal
Abort request, port 2. See AR3.
Abort request, port 1. See AR3.
Abort request, port 0. See AR3.
Reserved, should be cleared.
0 Default reset value.
1 Indicates to the CPU that the GCI controller has transmitted the previous monitor channel
Abort, port 3.
0 Default reset value.
1 Indicates to the CPU that the GCI controller has aborted the current message. This bit is
Abort, port 2. See AB3.
on the E bit. Automatically cleared by the monitor channel controller on receiving an abort, that is,
when PGMTS[AB] is set.
information. Automatically cleared by the CPU reading the register. The clearing of this bit by reading
this register also clears the aperiodic GMT interrupt.
automatically cleared by the CPU reading the register. When the GCI controller sets this bit, it also
clears the AR bit in the PGMTA register, the ACK bit in the GMTS register, and the L and R bits in the
PnGMT register.
Reset
Field ACK3
Addr
R/W
Chapter 13. Physical Layer Interface Controller (PLIC)
7
Table 13-10. PGMTS Field Descriptions
Table 13-9. PGMTA Field Descriptions
ACK2
6
ACK1
5
ACK0
MBAR + 0x371
0000_0000
Read Only
4
Description
Description
AB3
3
AB2
2
AB1
1
AB0
0
PLIC Registers
13-27
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