MOD5272-100IR NetBurner Inc, MOD5272-100IR Datasheet - Page 325

• Manufacturer Part Number: MOD5272-100IR
• Description: PROCESSOR MODULE FLASH MOD5272
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5272-100IR

• Module/board Type: Processor Module
• Ethernet Connection Type: 10/100 Ethernet Port RJ-45
• Operating Voltage: 3.3 V
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MOD5272
• For Use With: 528-1001 - KIT DEVELOP NETWORK FOR MOD5272
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 528-1008

MOTOROLA
13.5.17 GCI C/I Channel Transmit Registers
All bits in these registers are read/write and are cleared on hardware or software reset.
The PnGCIT registers are 8-bit registers containing the monitor channel bits to be
transmitted for each of the four ports on the MCF5272.
13.5.18 GCI C/I Channel Transmit Status Register
All bits in this register are read only and are cleared on hardware or software reset.
The PGCITSR register is an 8-bit register containing the C/I channel status bits for each of
the four transmit ports on the MCF5272.
Reset
Reset
31–29, 23–21,
27–24, 19–16,
Chan
Chan
Field
Field
28, 20, 12, 4
Addr
R/W
R/W
15–13, 7–5
11–8, 3–0
Bits
31
15
(PGCITSR)
Figure 13-29. GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT)
(P0GCIT–P3GCIT)
—
—
C3–C0 C/I bits. The CPU writes C/I data to be transmitted, on the GCI or SCIT channel 0, into
Name
—
R
MBAR + 0x378 (P0GCIT), 0x379 (P1GCIT), 0x37A (P3GCIT), 0x37B (P4GCIT)
29
13
Table 13-12. P0GCIT–P3GCIT Field Descriptions
Chapter 13. Physical Layer Interface Controller (PLIC)
Reserved, should be cleared.
Ready. This bit is set, by the CPU to indicate to the C/I channel controller that data is ready
for transmission. The transition of this bit from a 0 to a 1 starts the C/I state machine which
responds with the ACK bit once transmission of two successive C/I words is complete.
This bit is automatically cleared by the GCI controller when it generates a transmit
acknowledge (ACK bit in PGCITSR register). The clearing of this bit by reading this
register also clears the aperiodic GCT interrupt.
these positions. The CPU must ensure that this data is not overwritten before it has been
transmitted the required minimum amount of times, that is, so any change is detected and
confirmed by a receiver. A maskable interrupt is generated when this data has been
successfully transmitted
28
12
R
R
P0GCIT
P2GCIT
C3
C3
27
11
C2
C2
26
10
0000_0000_0000_0000
0000_0000_0000_0000
C1
C1
25
9
Read/Write
Read/Write
C0
C0
24
8
23
7
Description
—
—
21
5
20
R
R
P1GCIT
P3GCIT
4
C3
C3
19
3
C2
C2
18
PLIC Registers
2
C1
C1
17
1
13-29
C0
C0
16
0