MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 172

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
edges has expired. The signal SAS is provided as a status output to indicate which BCLK
rising edge the processor begins to sample the termination signals. If this mode is dis-
TBI ASSERTED
1) SET R/W TO READ
2) DRIVE ADDRESS ON A31–A0
3) DRIVE UP A1–UPA0, TT1–TT0, TM2–TM0,
4) DRIVE SIZ1–SIZ0 TO LINE
5) ASSERT TS FOR ONE BCLK
6) ASSERT TIP
7) ASSERT SAS IMMEDIATELY IF
1) REGISTER DATA
2) SAMPLE TBI AND TCI
3) INCREMENT A3–A2 IF CLA ASSERTED
CIOUT, TLN1–TLN0, LOCK, LOCKE, BS3–BS0
ACKNOWLEDGE TERMINATION IGNORE
STATE CAPABILITY DISABLED. ELSE,
ASSERT SAS AFTER READ PRIMARY
IGNORE STATE COUNTER HAS EXPIRED
1) ASSERT SAS IMMEDIATELY IF
1) REGISTER DATA
2) INCREMENT A3–A2 IF CLA
1) NEGATE LOCK, LOCKE IF
1) NEGATE TIP OR START NEXT
ACKNOWLEDGE TERMINATION
IGNORE STATE CAPABILITY
DISABLED. ELSE, ASSERT SAS
AFTER READ SECONDARY
IGNORE STATE COUNTER HAS
EXPIRED.
ASSERTED
NECESSARY
CYCLE
PROCESSOR
4 LW DONE
Figure 7-14. Line Read Cycle Flowchart
TBI NEGATED
M68060 USER’S MANUAL
CONTINUE WITH FIG. 7-16
1) DECODE ADDRESS
2) PLACE DATA ON D31–D0
3) ASSERT TA FOR ONE BCLK
4) ASSERT CLA TO INCREMENT A3–A2
1) DECODE ADDRESS
2) PLACE DATA ON D31–D0
3) ASSERT TA FOR ONE BCLK
4) ASSERT CLA TO INCREMENT A3–A2
5) ASSERT TBI OR TCI AS NEEDED
1) THREE-STATE D31–D0
4 LW NOT DONE
SYSTEM
Bus Operation
7-17