MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 71

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Memory Management Unit
Figure 4-1 illustrates the MMUs contained in the two memory units, one for instructions (sup-
porting instruction prefetches) and one for data (supporting all other accesses). Each MMU
contains a 64-entry ATC, two transparent translation registers (TTRs), and control logic. The
ATCs hold recently used logical to physical address translations, cache mode and protec-
tion information, and whether or not the page has been written. The TTRs are used for defin-
ing the cache modes, enabling protection modes and defining user page attributes for large
regions of untranslated address space. Each MMU also allows enabling a default cache
mode, protection, and user page attributes for address regions not covered by the ATC or
TTRs.
One of the principal functions of the MMU is to provide logical to physical address translation
using translation tables stored in memory. As an MMU receives a request from the corre-
sponding pipe unit, its ATC is searched for the translation, using the upper logical address
bits as a tag. If the translation is resident (or one of the TTRs hit causing transparent trans-
lation), the MMU provides the physical address for the corresponding cache lookup. If the
translation is not in the ATC (and the TTRs miss), then a table search is done using trans-
lation tables stored in memory. When the translation is obtained, it is used for the cache
lookup, and is placed in the ATC for future use. The table search is performed automatically
by the MC68060 using on-chip logic.
4-2
EXECUTION UNIT
EXECUTE
FETCH
FLOATING-
EA
FP
POINT
UNIT
OC
EX
BRANCH
CACHE
pOEP
DATA AVAILABLE
CALCULATE
EXECUTE
WRITE-BACK
DECODE
FETCH
INT
EA
EA
INSTRUCTION FETCH UNIT
INSTRUCTION
INTEGER UNIT
BUFFER
OC
DS
AG
EX
Figure 4-1. Memory Management Unit
sOEP
CALCULATE
DECODE
EXECUTE
INSTRUCTION
FETCH
CALCULATE
INT
DECODE
EA
EA
FETCH
EARLY
IA
M68060 USER’S MANUAL
OPERAND DATA BUS
AG
DS
OC
EX
IB
IAG
IED
IC
WB
DA
INSTRUCTION
INSTRUCTION MEMORY UNIT
DATA
ATC
ATC
DATA MEMORY UNIT
INSTRUCTION
CONTROLLER
CONTROLLER
CACHE
CACHE
DATA
INSTRUCTION
CACHE
CACHE
DATA
U
C
O
N
R
O
R
B
S
T
L
L
E
MOTOROLA
CONTROL
ADDRESS
DATA