MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 41

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
EORI to CCR Source
DIVS, DIVSL Destination
DIVU, DIVUL Destination
EORI to SR
Opcode
FDBcc 2
CPUSH
CMP2
CMPM
CMPA
FCMP
EXTB
FABS
FADD
CMPI
DBcc
EORI
CMP
FBcc
FDIV
EOR
EXG
CLR
EXT
2
0 ˘ Destination
Destination – Source ˘ cc
Destination – Source
Destination – Immediate Data
Compare Rn < LB or Rn > UB
If supervisor state
else TRAP
If condition false
Source
Immediate Data
If supervisor state
else TRAP
Rx ¯ ˘ Ry
Destination Sign – Extended ˘ Destination
Absolute Value of Source ˘ FPn
Source + FPn ˘ FPn
If condition true
FPn – Source
If condition true
else Dn – 1 ˘ Dn
FPn
Destination – Source ˘ cc
Source ˘ FPn
and Set Condition Codes
then if data cache push selected dirty data
cache lines; invalidate selected cache lines
then (Dn–1 ˘ Dn;
then Source
then PC + d n ˘ PC
then no operation
if Dn
else execute next instruction
Table 1-3. Instruction Set Summary (Continued)
Destination ˘ Destination
CCR ˘ CCR
Source ˘ Destination
Source ˘ Destination
–1
If Dn
then PC + d n ˘ PC
Destination ˘ Destination
SR ˘ SR
–1
Operation
then PC + d n ˘ PC)
M68060 USER’S MANUAL
CMP <ea>,Dn
CMPM (Ay)+,(Ax)+
CMP2 <ea>,Rn
CPUSHL <caches>, (An)
CPUSHP <caches>, (An)
CPUSHA <caches>
DBcc Dn,<label>
DIVS.W <ea>,Dn32
DIVS.L <ea>,Dq32
DIVS.L <ea>,Dr:Dq64 32 ˘ 32r:32q
DIVSL.L <ea>,Dr:Dq 32 32 ˘ 32r:32q
DIVU.W <ea>,Dn32
DIVU.L <ea>,Dq32
DIVU.L <ea>,Dr:Dq64 32 ˘ 32r:32q
DIVUL.L <ea>,Dr:Dq32 32 ˘ 32r:32q
EORI #<data>,CCR
EORI #<data>,SR
EXG Dx,Dy
EXG Ax,Ay
EXG Dx,Ay
EXG Ay,Dx
EXT.W Dnextend byte to word
EXT.L L Dnextend word to long word
EXTB.L Dn extend byte to long word
FABS.<fmt> <ea>,FPn
FABS.X FPm,FPn
FABS.X FPn
FrABS.<fmt> <ea>,FPn 3
FrABS.X FPm,FPn3
FrABS.X FPn3
FADD.<fmt> <ea>,FPn
FADD.X FPm,FPn
FrADD.<fmt> <ea>,FPn 3
FrADD.X FPm,FPn3
FBcc.SIZE <label>
FCMP.<fmt> <ea>,FPn
FCMP.X FPm,FPn
FDBcc Dn,<label>
FDIV.<fmt> <ea>,FPn
FDIV.X FPm,FPn
FrDIV.<fmt> <ea>,FPn
FrDIV.X FPm,FPn
CLR <ea>
CMPA <ea>,An
CMPI #<data>,<ea>
EOR Dn,<ea>
EORI #<data>,<ea>
Syntax
3
32 ˘ 32q
32 ˘ 32q
16 ˘ 16r:16q
16 ˘ 16r:16q
3
Introduction
1-17
2
2